Grant of Patent

Ethernity Networks Ltd (AIM: ENET.L; OTCMKTS: ENETF), a leading supplier of data processing and Passive Optical Network ("PON") semiconductor technology for networking appliances, is pleased to announce that it has received confirmation from the Company's US patent attorney that the United States Patent and Trademark Office has granted Ethernity's U.S Patent No. 12425341 (the "Patent"), titled "A method for routing using longest prefix matching" ("LPM"). The Company announced on 20 June 2025 that a notice of allowance had been issued in relation to the Patent application.

The Patent covers the implementation of a highly optimized method for routing using an LPM algorithm, designed to support hundreds of thousands of routes in few clock cycles, while eliminating the need for costly external components such as TCAM (Ternary Content Addressable Memory). This is achieved through Ethernity's unique firmware, which is embedded into the Company's pipeline data processor.

The algorithm was originally developed to form the corner stone of a new ultra highspeed networking design and then was integrated to become part of Ethernity's existing UEP offering and is fully applicable for ASIC implementation, offering a scalable and efficient approach to high-performance routing within integrated networking platforms. In essence, this Patent significantly strengthens the Company's intellectual property portfolio, reinforcing its position as a technology leader in data processing for routing applications.

The Patent complements and enhances the Company's planned ASSP (Application-Specific Standard Product) offering, which is designed to support Layer 3 MPLS routing capabilities in addition to standard Carrier Ethernet features. This Patent builds upon Ethernity's differentiated technology stack, which already includes its patented wireless link bonding and integrated PON functionality. Intellectual property protected by patents is critically important for Tier-1 OEMs, as it safeguards their deployments against potential intellectual property infringement claims, ensuring greater legal and commercial security.

While initially integrated into the UEP product, the patented design's code is optimized for significantly higher performance, capable of operating at 10x the throughput of the UEP design. This speed translates into exceptional lookup times: searching 100,000 IP prefixes in 70ns (FPGA) and 17ns (mid-range ASIC) and dropping to just a few nanoseconds for routes below 10,000. This capability allows it to be used as a standalone IP for extremely low-latency ASIC designs

Together, these innovations position the Company to deliver a highly integrated and cost-effective silicon solutions that meets the evolving needs of OEMs and service providers looking for advanced, scalable, and programmable access network platforms.